The present invention relates to the field of manufacturing semiconductor devices, and more particularly, to an improved complementary metal oxide semiconductor field effect transistor (CMOSFET).
An important aim of ongoing research in the semiconductor industry is increasing semiconductor performance while decreasing the size of semiconductor devices. Planar transistors, such as metal oxide semiconductor field effect transistors (MOSFET) are particularly well suited for use in high-density integrated circuits. As the size of the MOSFET decreases and the density of the devices increases, the demands of maintaining the electrical isolation of adjacent transistors increases.
The use of shallow trench isolation (STI) significantly shrinks the area needed to isolate transistors and thereby provides higher device density than local oxidation of silicon (LOCOS). STI also provides superior latch-up immunity, smaller channel width encroachment, and improved planarity. The use of STI techniques also eliminates the bird""s beak frequently encountered with LOCOS.
Strained silicon technology allows the formation of higher speed devices. Strained-silicon transistors are created by depositing a graded layer of silicon germanium (SiGe) on a bulk silicon wafer. A thin layer of silicon is subsequently deposited on the SiGe layer. The distance between atoms in the SiGe crystal lattice is greater than the distance between atoms in an ordinary silicon lattice. Because there is a natural tendency of atoms inside different crystals to align with one another when a second crystal is formed over a first crystal, when silicon is deposited on top of SiGe the silicon crystal lattice tends to stretch or xe2x80x9cstrainxe2x80x9d to align the silicon atoms with the atoms in the SiGe layer. Electrons in the strained silicon experience less resistance and flow up to 80% faster than in unstrained silicon.
There are two general types of MOS transistors, N-channel MOS (NMOS) formed with n-type source and drain regions in a p-type wafer, and P-channel MOS (PMOS) formed with p-type source and drain regions. NMOS transistors conduct electrons through the transistor channel, while PMOS transistors conduct holes through the transistor channel. Typically, the source and drain regions of the transistors are doped with phosphorous or arsenic to form n-type source/drain regions, while boron doping is used to form p-type source/drain regions.
CMOS transistors, which comprise N- and P-channel MOS transistors on the same substrate, suffer from imbalance. The imbalance is due to electron mobility being greater than hole mobility in the channel region. Therefore, NMOS transistors are faster than PMOS transistors. Typically, NMOS transistors are about 2 to about 2.5 times faster than PMOS transistors.
The problem of imbalance in CMOS devices is further exacerbated in CMOS devices comprising strained silicon channels. Strained silicon does not enhance hole mobility in PMOS transistors as much as it does electron mobility in NMOS transistors. Therefore, a CMOS device comprising strained silicon channels is more unbalanced than a CMOS transistor with conventional crystalline silicon channels.
The term semiconductor devices, as used herein, is not to be limited to the specifically disclosed embodiments. Semiconductor devices, as used herein, include a wide variety of electronic devices including flip chips, flip chip/package assemblies, transistors, capacitors, microprocessors, random access memories, etc. In general, semiconductor devices refer to any electrical device comprising a semiconductor.
There exists a need in the semiconductor device art to provide CMOS transistors, which combine more closely balanced PMOS and NMOS transistors with the increased speed of strained silicon. There exists a need in this art to provide smaller devices. There exists a need in this art to combine higher speed and smaller device-size to provide a more balanced CMOS transistor.
These and other needs are met by embodiments of the present invention, which provide a semiconductor device comprising a semiconductor substrate comprising a silicon germanium (SiGe) layer formed on a base layer. A plurality of field effect transistors (FET) including at least one first FET and at least one second FET are formed on the semiconductor substrate. The first FET comprises a gate electrode formed over the SiGe layer, and a gate oxide layer interposed between the gate electrode and the SiGe layer, wherein the gate oxide layer is formed immediately adjacent to and in contact with the SiGe layer. The second FET comprises a silicon layer formed on the SiGe layer, a gate oxide layer formed on the silicon layer, and a gate electrode formed on the gate oxide layer.
The earlier stated needs are also met by certain embodiments of the instant invention, which provide a method of manufacturing semiconductor devices comprising providing a semiconductor substrate comprising a SiGe layer formed on a base layer and a silicon layer formed on the SiGe layer. The semiconductor substrate comprises first regions and second regions spaced apart from each other by interposed isolation regions. At least a portion of the silicon layer is selectively removed only in the first region. Dopant is implanted in the first and second regions. A gate oxide layer is formed in the first and second regions and a gate electrode layer is formed over the gate oxide layer.
This invention addresses the needs for a higher-speed CMOS device with improved balance between the PMOS transistor and the NMOS transistor. The present invention allows the formation of smaller-sized CMOS transistors with improved performance.